Datasheet AD9652 (Analog Devices) - 17
| 制造商 | Analog Devices |
| 描述 | 16-bit, 310 MSPS, 3.3/1.8 V Dual Analog-to-Digital Converter (ADC) |
| 页数 / 页 | 37 / 17 — AD9652. Data Sheet. 140. 120. 100. SNRFS (dB), –40°C. SNRFS (dB), +25°C. … |
| 修订版 | C |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
AD9652. Data Sheet. 140. 120. 100. SNRFS (dB), –40°C. SNRFS (dB), +25°C. SNRFS (dB), +85°C. SFDR (dBFS), –40°C. SFDR (dBFS), +25°C

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AD9652 Data Sheet 78 140 78 140 76 76 120 120 74 74 72 100 SNRFS (dB), –40°C 72 100 SNRFS (dB), –40°C SNRFS (dB), +25°C SNRFS (dB), +25°C SNRFS (dB), +85°C SNRFS (dB), +85°C B) B) B) 70 B) 70 d SFDR (dBFS), –40°C d d SFDR (dBFS), –40°C d SFDR (dBFS), +25°C 80 SFDR (dBFS), +25°C 80 SFDR (dBFS), +85°C SFDR (dBFS), +85°C NR ( 68 DR ( NR ( 68 DR ( S SFDR (dBc), –40°C F SFDR (dBc), –40°C F SFDR (dBc), +25°C S S SFDR (dBc), +25°C S SFDR (dBc), +85°C SFDR (dBc), +85°C 66 60 66 60 64 64 40 40 62 62 60 20 60 20 –80 –60 –40 –20 0
015
–80 –60 –40 –20 0
115
AIN (–dBFS) A
12169-
IN (–dBFS)
12169- Figure 24. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with Figure 27. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = fIN = 90.1 MHz, VREF = 1.0 V, Over Temperature, Dither Off 90.1 MHz, VREF = 1.0 V, Over Temperature, Dither On
76 110 76 110 SNRFS SNRFS (NYQUIST SETTING 1) (NYQUIST SETTING 1) 74 106 74 106 SNRFS SNRFS (NYQUIST SETTING 2) (NYQUIST SETTING 2) 72 SNRFS 102 72 SNRFS 102 (NYQUIST SETTING 3) (NYQUIST SETTING 3) 70 98 70 98 68 94 68 94 B) Bc) B) B) d d d d 66 90 66 90 NR ( DR ( NR ( DR ( S F S F 64 86 S 64 86 S 62 82 62 82 SFDR SFDR 60 (NYQUIST SETTING 1) 78 60 (NYQUIST SETTING 1) 78 SFDR SFDR 58 (NYQUIST SETTING 2) 74 58 (NYQUIST SETTING 2) 74 SFDR SFDR (NYQUIST SETTING 3) (NYQUIST SETTING 3) 56 70 56 70 0 50 100 150 200 250 300 350 400 450 500 550
116
0 50 100 150 200 250 300 350 400 450 500 550
016
fIN (MHz) f
12169-
IN (MHz)
12169- Figure 25. Single Tone SNR/SFDR vs. Input Frequency (fIN), Figure 28. Single Tone SNR/SFDR vs. Input Frequency (fIN), Amplitude = −1 dBFS, VREF = 1.25 V Amplitude =−1 dBFS, VREF = 1.0 V
76 110 76 110 74 SNRFS 106 74 106 (NYQUIST SETTING 1) SNRFS (NYQUIST SETTING 1) 72 SNRFS 102 72 SNRFS 102 (NYQUIST SETTING 2) (NYQUIST SETTING 2) SNRFS 70 (NYQUIST SETTING 3) 98 70 SNRFS 98 (NYQUIST SETTING 3) 68 94 68 94 B) Bc) B) Bc) d d d d 66 90 66 90 NR ( DR ( NR ( DR ( S F S F 64 86 S 64 86 S 62 82 62 82 SFDR SFDR 60 (NYQUIST SETTING 1) 78 60 (NYQUIST SETTING 1) 78 SFDR SFDR 58 (NYQUIST SETTING 2) 74 58 (NYQUIST SETTING 2) 74 SFDR SFDR (NYQUIST SETTING 3) (NYQUIST SETTING 3) 56 70 56 70 0 50 100 150 200 250 300 350 400 450 500 550
017
0 50 100 150 200 250 300 350 400 450 500 550
117
fIN (MHz) f
12169-
IN (MHz)
12169- Figure 26. Single Tone SNR/SFDR vs. Input Frequency (fIN), Figure 29. Single Tone SNR/SFDR vs. Input Frequency (fIN), Amplitude = −7 dBFS, VREF = 1.25 V Amplitude = −7 dBFS, VREF = 1.0 V Rev. B | Page 16 of 36 Document Outline Features Applications Functional Block Diagram General Description Product Highlights Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Input Common Mode Common-Mode Voltage Servo Dither Large Signal Fast Fourier Transform Small Signal FFT Static Linearity Differential Input Configurations Voltage Reference Internal Reference Connection External Reference Operation Clock Input Considerations Clock Input Options Input Clock Divider Clock Duty Cycle Jitter Considerations Power Dissipation and Standby Mode Internal Background Calibration Digital Outputs Timing Data Clock Output ADC Overrange Fast Threshold Detection (FDA/FDB) Serial Port Interface Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels Transfer Register Map Channel Specific Registers Memory Map Register Table Applications Information Design Guidelines Power and Ground Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide