Datasheet Analog Devices AD8075ARUZ — 数据表

a
FEATURES
Dual Supply ⴞ5 V
High-Speed Fully Buffered Inputs and Outputs
600 MHz Bandwidth (-3 dB) 200 mV p-p
500 MHz Bandwidth (-3 dB) 2 V p-p
1600 V/␮s Slew Rate, G = +1
1350 V/␮s Slew Rate, G = +2
Fast Settling Time: 4 ns
Low Supply Current: V DGND + ~2.0 V and enabled for
VOE < VDGND + 0.8 V. TTL logic levels are expected. The following restrictions are placed upon the digital ground potential:
3.5 V ≤ VAVCC - VDGND ≤ 12 V
VDGND ≥ VAVEE The architecture of the output buffer is such that the output
voltage can swing to within ~2.3 V of either rail. For example, if
the output need swing only 2 V, then the buffers could be operated on dual 3.5 V or single 7 V supplies. It is cautioned that
saturation effects may become noticeable when the output swings
within 2.6 V of either rail. The system designer may opt to
use this characteristic to his or her advantage by using the
soft-saturation regime, (2.2 V-2.6 V from the supply rails), to
tame excessive overshoot. The designer is cautioned that a
charge storage associated time delay of several nanoseconds is
incurred when recovering from soft-saturation. This effect
results in longer settling tails. -9- AD8074/AD8075 …