Datasheet Texas Instruments CD4020BE — 数据表

制造商Texas Instruments
系列CD4020B
零件号CD4020BE
Datasheet Texas Instruments CD4020BE

CMOS 14级纹波传送二进制计数器/除法器16-PDIP -55至125

数据表

CD4020B, CD4024B, CD4040B TYPES datasheet
PDF, 1.6 Mb, 修订版: D, 档案已发布: Dec 11, 2003
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin16
Package TypeN
Industry STD TermPDIP
JEDEC CodeR-PDIP-T
Package QTY25
CarrierTUBE
Device MarkingCD4020BE
Width (mm)6.35
Length (mm)19.3
Thickness (mm)3.9
Pitch (mm)2.54
Max Height (mm)5.08
Mechanical Data下载

参数化

Approx. price0.11 | 1ku US$
Bits12
F @ nom voltage(Max)8 MHz
FunctionCounter
ICC @ nom voltage(Max)0.03 mA
IOH(Max)-1.5 mA
IOL(Max)1.5 mA
Operating temperature range-55 to 125 C
Package GroupPDIP|16,SO|16,TSSOP|16
Package size: mm2:W x LSee datasheet (PDIP),16SO: 80 mm2: 7.8 x 10.2 (SO|16),16TSSOP: 22 mm2: 4.4 x 5 (TSSOP|16) PKG
RatingCatalog
Technology FamilyCD4000
TypeBinary
VCC(Max)18 V
VCC(Min)3 V
Voltage(Nom)5,10,15 V
tpd @ nom Voltage(Max)160 ns

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: 14-24-LOGIC-EVM
    Generic Logic EVM Supporting 14 through 24 Pin PW; DB; D; DW; NS; P; N; and DGV Packages
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics
    PDF, 188 Kb, 档案已发布: Dec 3, 2001
    Both buffered and unbuffered CMOS B-series gates inverters and high-current IC products are available from TI. Each product classification has application advantages in appropriate logic-system designs. Many CMOS suppliers have concentrated on promoting buffered B-series products with applications literature focusing on the attributes and use of the buffered types. This practice has left an imb
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, 档案已发布: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, 修订版: C, 档案已发布: Dec 2, 2015

模型线

制造商分类

  • Semiconductors > Logic > Specialty logic > Counter/arithmetic/parity function